CPU Architecture & Authority Control
General register designations. ______________________________________________________________________________________________ Till physical address & authority control ___________________________________________________________________________________________________ Segment Descriptor : 8 Byte size Content ___________________________________________________________________________________________________ Segment Descriptor Table _asm lgdt [GDT] GDTR __________________________________________________________________________________________ x64 __________________________________________________________________________________________ ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━ explains Till RAM & Authority control (of Intel Processor) -------------------------------------------------------------------------------------------- Process → Segment Descriptor → Paging → RAM (physical address)